The landscape of electronic design is being transformed, driven by generative AI, digital twin, and advanced-node technologies. Cadence is at the forefront of this transformation, offering a comprehensive suite of chips-to-system solutions that empower our partners to innovate faster, with greater efficiency and productivity. We will discuss how the innovations in Cadence’s AI-driven solutions for electronic and systems design are helping customers create their amazing products and solutions.

Dr. Chin-Chi Teng
Senior Vice President and General Manager, Digital & Signoff Group, Cadence

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Dr. Chin-Chi Teng

Dr. Chin-Chi Teng has served as Senior Vice President and General Manager of the Digital and Signoff Group (DSG) of Cadence since 2018. Prior to this role, Teng held senior leadership positions in research and development in digital implementation.

Dr. Teng joined Cadence in 2002 via the acquisition of Silicon Perspective Corporation and subsequently led various research and development groups. He brought deep technical knowledge and more than 20 years of industry and academic experience to his role as leader of the IC Digital group.

Dr. Teng holds a BS in electrical engineering from the National Taiwan University and an MS and PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He holds seven patents, and has written many EDA papers, several deep learning papers, and a book, Electrothermal Analysis of VLSI Systems.

Metanoia is the only company providing 5G O-RAN chip solutions in Taiwan. Specializing in software-defined radio (SDR) technology, Metanoia aims to offer innovative solutions for the 5G Open RAN infrastructure. Their advanced technologies enable cost-effective and efficient deployment of O-RU, disrupting traditional models. This presentation also discusses the ASIC and COT models utilized in Metanoia’s design flow. 

Overall, Metanoia is positioned to play a pivotal role in the evolution of 5G technology, driving advancements in network architecture and contributing to the growing demand for robust and efficient wireless communication solutions.

C.Y. Chang
VP of Hardware Technology, Metanoia Communications Inc. (義傳科技 技術副總 張俊彥)

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C.Y. Chang

Since joining Metanoia in 2003 as an engineer, C.Y Chang has contributed to the design of many communications IC chips in Metanoia, and this for different markets, starting with wireline broadband, and more recently for 5G Radio Access Network. His dedication over the years helped him to gain valuable experience in both digital and analog IC design and tape-out and positioned to become the leader of the IC Hardware and Operations group of Metanoia.

Prior to joining Metanoia, C.Y worked in a Power IC company, where he gained significant experience in both analog and mixed IC design and he also managed all tape-out jobs. His expertise in these areas has been invaluable to Metanoia in the highly competitive semiconductor industry. More recently, C.Y has been instrumental in the development and validation of Metanoia 5G chips, its Digital Front End chip and sub 6GHz RF Transceiver. Under his leadership, the company’s 5G solutions have been successfully brought to market and with exceptional quality.

C.Y holds a BSEE & MSEE from National Yang Ming Chiao Tung University, one of Taiwan’s top universities. His academic background, combined with his extensive industry experience, has positioned him as a leader in Hardware design.

Accelerating AI-Driven Digital Twins of Data Centers

Ben Gu
Corporate VP of R&D Multi-Physics System Analysis, Cadence (多物理系統分析事業群 全球研發副總裁)

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Ben Gu

As the leader of Multi-Physics System Analysis Group in Cadence, Ben oversees RnD, Product Engineering, Product Validation of all the system level products in Cadence, including the recently acquired data center digital twin products, the recently launched CFD products, the Fidelity CFD solver, the Clarity 3D FEM full wave Solver, Celsius Thermal Solver as well as Sigrity, Voltus and ESD products. Additionally, he is also responsible for the strategy and M&A of those areas. Prior to taking this role, Ben has been with various RnD leadership positions in Cadence since 2012, including RnD head of Voltus, Clarity, Sigrity, etc. Ben's main contributions in Cadence include: * Led the development of Cadence's first system analysis product, Clarity 3D solver. The revolutionary technologies inside Clarity, massive parellelization and elastic computing, provide customers unprecedented performance improvements over competition (> 10x) and virtually unlimited capacity. * Led the development of Cadence's electro-thermal simulation product, Celsius thermal solver. The breakthrough technologies inside Celsius, massive parellelization and seamless integration with power simulation solutions, provide customers the first completely integrated electro thermal simulation tool for the increasingly important thermal challenges in 3DIC, SoC, package, and PCB designs. * Led the development of Cadence's fully distributed power grid simulator, Voltus and Voltus-Fi, and improved the Voltus business by several times in less than 4 years. Before Cadence, Ben had been with Magma, Freescale, and Motorola, developing simulation related EDA products. Ben received numerous awards including the Cadence Corporate Innovation Award. He has published numerous research papers, and received the prestigious IEEE Donald Peterson Best Paper Awards in 2016, and holds 5 U.S. patents. Ben received a Bachelor of Science degree in electrical engineering from Shanghai Jiaotong Uuniversity and M.S. degree in electrical engineering from the Penn State University.

Eunice Chiu
Vice President and General Manager Taiwan, NVIDIA (輝達 全球副總裁暨台灣區總經理 邱麗孟)

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Eunice Chiu

To effectively mitigate failures in advanced IC, it’s critical to understand potential failures. With an understanding of potential failures and correctly identify high impact and critical design elements, engineers can then validate the design and the mitigation scheme through various verification techniques such as simulation, fault injection, and accelerated radiation testing. Commonly deployed mitigation schemes such as triple module redundancy and design considerations will also be addressed to ensure the common EDA’s automated feature is deployed adequately.

Chen Wei Tseng
Technical Manager,SGS

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Chen Wei Tseng

SGS technical manager

Developed and tested mitigation and verification solution at Xilinx A&D group

Delivered functional safety solution for commercial applications such as server, telecom, and automotive

Crafted COTS FPGA solution for aerospace OBC unit

Validated different mitigation schemes developed by EDA through accelerated radiation tests 

Owner of over 5 US patents 

Jeff Chang
SGS

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Jeff Chang

1. GUC Advanced Package Technology (APT) Development

2. 3Dblox - 3D Design Intent Description Language

3. 3DIC Implementation Flow with 3Dblox & Integrity 3DIC 

4. Benefits of Using 3Dblox/iHDB in Sign-off Flow

5. Integrity 3DIC Checking

6. Hybrid Bonding/PG Mesh Co-Design

7. Optimized TSV Macro Array Structure 

8. An Efficient Method for 3DIC DECAP Evaluation

9. Voltus 3DIR Solver Capacity Improvement

10. Using Voltus SGUI for 3DIR Result Review

Hubert Jiang
Assistant Manager, GUC

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Hubert Jiang

Hubert is deputy manager in Company GUC.

Hubert has 5 years experience in Digital design IR flow.

Apply iDSPF format to investigate the effects of parasitics on circuits using Virtuoso Parasitic Aware Design in the analog design simulation environments (ADE Explorer and ADE Assembler) and Virtuoso Schematic Editor (Schematics L/XL) applications.

Echo Hu
Deputy Technical Manger, Richtek

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Echo Hu

Echo is a Deputy Technical Manger in RichTek. 20 years’ experience in LPE/RC field. Responsible for back-End Analog Design Flow Worked for Cadence foundry support team over 15 years.

As Mixed-Signal ICs adopt newer technologies to enable a wide range of applications, the design of individual components and systems often require deeper insights to explore new architectures and to verify performance across all corners. In this presentation, we will explore how to extract complex metrics and identify trends in large IC simulation databases. We will demonstrate how to optimize multivariable IC designs with different techniques, in order to meet specifications in time and frequency domains. We will use MATLAB to directly control the setup of design variables and parameters in Cadence® Virtuoso®, programmatically run simulations, and analyze results. Finally, we will use surrogate optimization methods to improve the performance of transistor-level IC designs.

Highlights/key takeaways:

•In-depth mixed-signal data analysis and metrics extraction 

•IC design space exploration

•Multivariable optimization of IC designs

Phoebe Li
Assistant Manager, Terasoft

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Phoebe Li

• Phoebe Li is Assistant Manager at Terasoft.

• Responsible for technical support in the areas of signal processing, mixed signal verification, cross-platform language integration, etc.

PPA (Power, Performance and Area) convergence and TAT (Turn Around Time) reduction are the most important indexes during design implementation. In advanced process technology, the cross-stage PPA variations have become more unpredictable due to the complexity of designs. This mismatch will lead to unexpected congestion, timing and utilization rate which causes additional TAT. In the worst-case scenario, the project schedule can be delayed. Therefore, in recent years, the concept of Full-flow has gradually gained attention in RTL to GDS implementation. Once the correlation is handled well, the iterations between stages such as synthesis and P&R can be efficiently reduced. To reach full-flow, several techniques such as Genus iSpatial, Cerebus are introduced by Cadence. Through these solutions, we can achieve more accurate results than the legacy flow. However, in some cases, the hotspot and density correlations are still not as expected due to extremely complicated physical rules this work, we adopted Cadence PODV2 Turbo Place solution during design implementation. PODV2(place_opt_design V2) introduces new engine for run time reducing compared to the original POD (place_opt_design) engine. Furthermore, through PODV2, physical synthesis can easily reach P&R placement stage s quality. According to our real product results, we got correlated result through Genus synthesis to P&R with 10~30% full-flow runtime enhancem

Ching-Yu Shih
Senior Engineer, MediaTek

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Ching-Yu Shih

ChingYu is a design methodology engineer in MediaTek.

He has 7 years experience in physical implementation and logic synthesis.

He holds a master's degree in electrical engineering from National Chiao Tung University in Hshin-Chu, Taiwan.

Will Lin
Senior Manager, MediaTek

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Will Lin

Will Lin has a VLSI experience with 17 years and majorly focus on logic synthesis and low power design flow.

Will Lin also investigates RTL signoff and AI solution to explore higher design quality in recent years.​

The Tempus DRA Suite comprises five advanced timing analyses: aging robustness, voltage robustness, timing robustness, silicon prediction, and VT skew robustness. The suite’s advanced timing models enable design engineers to accurately analyze these effects with significantly reduced pessimism compared to traditional approaches such as derates or margins. Furthermore, design engineers may use the timing data to drive optimization and signoff closure using the Tempus ECO Option from within the Cadence Innovus Implementation System or using the Cadence Certus Closure Solution. This integrated approach ensures the best PPA and fastest closure from block-level to subsystem-level/full-chip design.

Louis Lin
Principal Product Engineer , Cadence

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Louis Lin

Louis is Tempus Principal Product Engineer Located in Taiwan.

Louis has joined Cadence for 3+ years, and have ~10years of STA experience.

His major focus is developing the Tempus/Tempus ECO tool/flow/methodology for advanced technologies.

Holds master’s and bachelor’s degrees in Electrical Engineering from NCTU University.

Nowadays, the digital design scale grows up sharply. Not only timing closure is a challenge, but also power closure. Before Voltus InsightAI rolls out, PD/IR always spends several iterations to fix IR problems with long turnaround time. In 2024, Cadence introduced an amazing solution ‘Voltus InsightAI’. It can help user to reduce the iteration and speed up the verification time. The PG enhancement of Voltus InsightAI will neither degrade timing nor induce any DRC violations. No doubt, Voltus InsightAI is a powerful tool for IR improvement automatically. We really appreciate Cadence can provide this amazing product.

Hung Liu
Engineer, Phison

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Hung Liu

Hung worked as a Power Integrity engineer in MediaTek

He now works at the Physical Design Verification team on Phison and is responsible for IR drop analysis.

Cerebrus FloorPlan Optimization is a powerful new generation AI of engine which can handle macros and STD cells' placement concurrently. It provides PPA (power, performance, area) improvements and greatly reduces the turnaround time to find an optimal floorplan, and shrink the area more effectively. In this presentation, we will introduce the attractions of Cerebrus FloorPlan Optimization in our case. We will also talk about the area for improvements and what is under working with Cadence now.

Will Lin
Manager, Realtek

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Will Lin

Will is a manager of physical design team in Realtek and has 13 years of physical design experience. In the past 5 years, Will’s work is focused on physical implementation flow Research and development.

Low-power design has become more challenging with the downscaling of technology. 

Cadence Cerebrus ML flow provides an automatic and reliable solution to reduce leakage power.

By using the FP-Opt flow, better PPA and UR can be achieved.

Welson Lin
Senior Engineer, Phison

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Welson Lin

Worked on PnR team in Phison Electronics Corp.

Executed physical design, analysis and verification for circuit design.

Currently, packages use Fan Out Multi Chip Module (FO-MCM), small bump diameters, high Tg and ultra-low K materials. When MCM and the coreless substrate warp in different directions during the heating cycle, this results in very high stress on the bumps. The traditional mass reflow (MR) flip chip bonding process is no longer suitable for this scenario. To overcome this problem, the TCB process is introduced. This process uses a soldering head to press large MCM areas, suppressing MCM warpage. The soldering head applies pressure along the Z-axis after the bumps have melted, reducing the bump height between the MCM and the coreless substrate. The warpage behavior of the substrate due to TCB process heating can be suppressed by vacuum adsorption to a ceramic carrier plate. This topic is utilized Cadence Celsius to build up the case and run stress warpage simulation to evaluate the Thermal Compression Bonding process. For the what if design to observe the warpage result with temperature aware conditions.

現今，封裝體採用 Fan Out Multi Chip Module (FO-MCM)、小凸塊直徑、高 Tg 和超低 K材料，當 MCM 與無核基板於加熱週期產生不同方向的翹曲，進而拉扯 bump 產生極高應力，以往透過熱迴流(mass reflow, MR)的 flip chip bond 製程已無法適用，為了克服這個問題，引入 TCB 製程，利用焊接頭對大面積的 MCM 進行壓合，抑制 MCM 翹曲問題，並且透過焊接頭，在 bump 融溶之後在 Z 軸施加壓力進行下壓，也可達到縮小 MCM 與無核基板之間的 bump 高度。因 TCB 製程加熱而造成基板的翹曲行為可透過下方的陶瓷載板的真空槽進行吸附並抑制基板的翹曲。基於現場實務考量，利用 Cadence，針對封裝載板進行真空槽孔大小、形狀、距離進行設計，並建置熱壓銲合(Thermal Compression Bonding, TCB)製程環境，模擬晶片與封裝載板於真空熱壓銲合製程中隨溫度變化之翹曲情形。 

Yu Chen Li
College of Semiconductor and Advanced Technology Research,NSYSU

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Yu Chen Li

TCB intern PE in ASE.

Focus on processing optimization in CoW(Chip on Wafer) 、Cos(Chip on Substrate).

Familiar with Cadence simulation tool for processing of TCB and Tooling design.

Second year of graduate school in Institute of Advanced Semiconductor Packaging and Testing

In the dynamic hardware design and verification sphere, achieving exhaustive test coverage amidst escalating complexity presents a formidable challenge. Learn how Cadence’s Verisium SimAI utilizes machine learning to scrutinize past regression outcomes, analyze the nature of remaining coverage holes, and correlate randomization events to design states around the remaining holes. The technology can also remove redundancy to efficiently use compute resources and target rare scenarios to hunt for difficult bugs. Maximize your verification productivity by incorporating SimAI in your verification cycle.

Anika Sunda
Sr Product Marketing Manager, Cadence

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Anika Sunda

Anika is a senior product marketing manager in the SVG group at cadence. Anika has 15 years of experience spanning product management, research development, and verification. She is responsible for business development and product marketing of Xcelium and Verisium products, helping bring Cadence's AI/Machine learning technology to the broader market. Holds master’s and bachelor’s degrees in Electronics from IIIT Bangalore.

In recent years, SmartPhone has great computing power advancement and could run games in high res and fps, but GPU capability depends. 

There are metrics ODM company and Gamer usually used to value GPU like power, performance and power efficiency, …,etc. 

Therefore, how to determine the metrics in pre-silicone stage, and then depend the results to have quick design iteration or software finetune becomes more important. 

In traditional method, designer usually pickup representative micro second scale frames from second or minute scale application for power profiling. 

The power profiling runtime of a frame usually takes over a week with commercial power signoff tool. 

However, this kind of runtime scale is not executable. Even designers complete all scenarios’ power profiling, they can only make changes on next generation.

In this work, we adopt DPA on GPU frame-level power profiling to achieve finishing micro second frame power calculation in 6 hours and still having 95% competitive accuracy in average.

Li-Cheng Zheng
Senior Engineer, MediaTek

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Li-Cheng Zheng

Li-Cheng is an engineer in a power flow team with the Mediatek. Li-Cheng has 4-year experience in CAD domains, especially for power analysis. His major focus is developing the RTL waste and Netlist power analysis tool, flow and methodology for advanced technologies. Receives master’s degree in Electrical Engineering from National Central University and bachelor’s degree in Computer Science Engineering from Yuan Ze University.